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Published June 2008 | Version Published
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A tunable concurrent 6-to-18 GHz phased-array system in CMOS

Creators

  • 1. ROR icon California Institute of Technology

Abstract

This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-to-18 GHz implemented in a 130nm CMOS process. The single receiver element with a 10-bit phase shifting resolution achieves a maximum phase error of 2.5° within a baseband amplitude variation of 1.5dB for an arbitrary target angle. This dense interpolation provides excellent phase error/offset calibration capability in the array. A 4-element electrical array pattern is measured at 6 GHz, 13.5 GHz and 18 GHz, showing a worst case peak-to-null ratio of 21.5dB. The EVM and phase noise improvements of the array compared with the single receiver element are also shown.

Additional Information

© 2008 IEEE. The authors would like to thank E. Keehr and J. Yoo of the California Institute of Technology, and J. DeFalco, R. Healy, and M. Sarcione of Raytheon for their technical discussions. The authors would also like to acknowledge Office of Naval Research for the support of this work through contract #N00014-04-C-0588.

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Additional details

Identifiers

Eprint ID
75761
Resolver ID
CaltechAUTHORS:20170405-171251898

Funding

Office of Naval Research (ONR)
N00014-04-C-0588

Dates

Created
2017-04-06
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Updated
2021-11-15
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