Pipelined Asynchronous Cache Design

This thesis describes the development of pipelined asynchronous cache memories. The work is done in the context of the performance characteristics of memories and transistor logic of a late 1990's high-performance asynchronous microprocessor. We describe the general framework of asynchronous memory systems, caching, and those system characteristics that make caching of growing importance and keep it an interesting research topic. Finally, we present the main contribution of this work, which is a latency-tolerating asynchronous cache micro-architecture suitable for asynchronous microprocessors. In Chapter Two, we present a case study of the Level 1 data and instruction caches for the Caltech MiniMIPS asynchronous microprocessor, currently under development at Caltech. The implementation is quasi-delay-insensitive in 0.6 micron scalable CMOS rules, with a logic latency of approximately 2 nanoseconds.