Published 1990
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VLSI Implementation of a High-Capacity Neural Network Associative Memory
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Abstract
In this paper we describe the VLSI design and testing of a high capacity associative memory which we call the exponential correlation associative memory (ECAM). The prototype 3µ-CMOS programmable chip is capable of storing 32 memory patterns of 24 bits each. The high capacity of the ECAM is partly due to the use of special exponentiation neurons, which are implemented via sub-threshold MOS transistors in this design. The prototype chip is capable of performing one associative recall in 3 µS.
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© 1990 Morgan Kaufmann. This work was supported in part by NSF grant No. MIP-8711568.Attached Files
Published - 217-vlsi-implementation-of-a-high-capacity-neural-network-associative-memory.pdf
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217-vlsi-implementation-of-a-high-capacity-neural-network-associative-memory.pdf
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- 63480
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- CaltechAUTHORS:20160107-161736867
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Funding
- NSF
- MIP-8711568
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2020-03-09Created from EPrint's datestamp field
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2019-10-03Created from EPrint's last_modified field
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- Advances in Neural Information Processing Systems
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- 2