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Published December 2005 | Version public
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Pipelining saturated accumulation

Creators

  • 1. ROR icon California Institute of Technology

Abstract

Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280MHz on a Xilinx Spartan-3 (XC3S-5000-4), the maximum frequency supported by the component's DCM.

Additional Information

© 2005 IEEE. Issue Date: 11-14 Dec. 2005. Date of Current Version: 10 January 2006. This research was funded in part by the NSF under grant CCR-0205471. Stephanie Chan was supported by the Marcella Bonsall SURF Fellowship. Karl Papadantonakis was supported by a Moore Fellowship. Scott Weber and Eylon Caspi developed early FPGA implementations of ADPCM which helped identify this challenge. Michael Wrighton provided VHDL coding and CAD tool usage tips.

Additional details

Identifiers

Eprint ID
24888
Resolver ID
CaltechAUTHORS:20110816-113648980

Funding

NSF
CCR-0205471
Marcella Bonsall SURF Fellowship
Moore Fellowship

Dates

Created
2011-09-14
Created from EPrint's datestamp field
Updated
2021-11-09
Created from EPrint's last_modified field

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Other Numbering System Identifier
8825611