CaltechAUTHORS
Published September 2006 | Version public
Book Section - Chapter Metadata-only

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices

Creators

  • 1. ROR icon Toshiba (Japan)
  • 2. ROR icon California Institute of Technology

Abstract

We present a novel 3D crossbar for future Network-on-a-Chip implementations. We introduce a routing algorithm for the 3D crossbar circuit and detail two specific 3D crossbar topologies. We evaluate the defect tolerance of the 3D crossbar and quantify the number of extra layers required to support arbitrary permutations as a function of the defect rate. Further, we estimate the circuit performance and advantages of the 3D crossbar circuit based on post-silicon devices.

Additional Information

© 2006 IEEE. Issue Date: Sept. 2006. Date of Current Version: 16 April 2007. The authors are grateful to Shinichi YASUDA and Dr. Tetsufumi TANAMOTO, Corporate R&D Center, Toshiba Corp., and Dr. Bipul C Paul and Dr. Masaoki OKAJIMA, Toshiba America Research, Inc., for helpful comments.

Additional details

Identifiers

Eprint ID
24476
Resolver ID
CaltechAUTHORS:20110720-093755059

Dates

Created
2011-07-21
Created from EPrint's datestamp field
Updated
2021-11-09
Created from EPrint's last_modified field

Caltech Custom Metadata

Other Numbering System Name
INSPEC Accession Number
Other Numbering System Identifier
9366008