CaltechAUTHORS
Published September 2012 | Version public
Book Section - Chapter Metadata-only

A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS

Creators

  • 1. ROR icon Rambus (United States)

Abstract

A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.

Additional Information

© 2012 IEEE.

Additional details

Identifiers

Eprint ID
73969
Resolver ID
CaltechAUTHORS:20170201-164230015

Dates

Created
2017-02-02
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Updated
2021-11-11
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