Published February 2011 | Version public
Book Section - Chapter

High-density IC chip integration with parylene pocket

  • 1. ROR icon California Institute of Technology

Abstract

We utilize the parylene pocket technology and develop a novel integration scheme that will allow us to connect more than 100 bonding pads on an area less than 5 mm × 5 mm with high efficiency. This packaging technique can also house any IC chip or discrete component and provide electrical connection to it. Here we use squeegee technique to connect each pad on the chip with the bonding pad on the pocket to achieve functionality because the chip that is to be integrated in this section has a very dense array and it is impractical and extremely difficult to connect everything manually. Devices testing are done by testing dummy chip integration and soaking test. Positive results prove that such parylene pocket packaging technique works well.

Additional Information

© 2011 IEEE. Date of Current Version: 12 September 2011. The authors would like to thank our lab manager, Trevor Roper, for his technical assistance in terms of device fabrication and our group members for fruitful discussions.

Additional details

Identifiers

Eprint ID
35275
Resolver ID
CaltechAUTHORS:20121105-083903340

Dates

Created
2012-11-14
Created from EPrint's datestamp field
Updated
2021-11-09
Created from EPrint's last_modified field

Caltech Custom Metadata

Other Numbering System Name
INSPEC Accession Number
Other Numbering System Identifier
12229794