A Methodology for Hierarchical Simulation and Verification of VLSI Systems

We present a hierarchical methodology for ensuring functionally correct VLSI designs. This methodology allows (1) a design be decomposed in such a way that more efficient simulation algorithms than those appeared in most one-level simulators can be employed, (2) abstraction of parts of a design may be made to reduce the complexity of the entire design. We first give computation models of VLSI designs. From these models , we derive appropriate algorithms and compare them to illustrate the power of our methodology. Finally we present the method for ensuring correctness of design at each hierarchical level and across different levels.